A Novel Ultra-Low Logic Step Fault-Tolerant Quantum Circuit Synthesis via Lattice Surgery
Chien-Tung Kuo, Cheng-En Tsai, Chung-Yang (Ric) Huang
A novel quantum circuit synthesis framework that converts quantum circuits to ZX Calculus, optimizes them, and produces fault-tolerant lattice surgery operations with 3D visualization and verification capabilities.
Resource-efficient and robust quantum federated learning via loss aggregation
Cheng-En Tsai, Hao-Chung Cheng
Submitted
A novel method that aggregates loss values instead of gradients in quantum federated learning, reducing communication overhead and quantum measurements by orders of magnitude while maintaining strong convergence under non-IID data distribution.
QSyn: A Developer-Friendly Quantum Circuit Synthesis Framework for NISQ Era and Beyond
Mu-Te Lau, Chin-Yi Cheng, et al., including Cheng-En Tsai and Chung-Yang (Ric) Huang
Developed a C++-based quantum circuit compilation framework that provides a unified environment for prototyping and evaluating quantum circuit synthesis algorithms, with robust developer tools including CI/CD and regression testing.
Configurable BCH Decoder for High-Speed Optical Interconnects
Oct 2025 β Jan 2026
Computer-Aided VLSI System Design
- Architected a multi-standard BCH decoder in Verilog supporting (63,51)/(255,239)/(1023,983) codes in hard/soft-decision modes, optimized via a unified GF multiplier with XOR-tree reduction and 8-lane shared ROM.
- Implemented the full RTL-to-GDSII flow using VCS and Innovus, delivering 1.58 mmΒ² core area, 14.7 mW power, and zero DRC/LVS violations.
ATΒ²-Optimized 32-bit Pipelined RISC-V Processor (RV32IC)
Apr 2025 β Jun 2025
Digital System Design
- Designed a 32-bit, 5-stage pipelined RISC-V processor (RV32I + C extension) with 2-way set-associative I/D caches and a hazard unit for data/control hazards via forwarding/stalls.
- Compared branch prediction and multiplier architectures via ATΒ² analysis, synthesizing in TSMC 0.13Β΅m at 3.0 ns cycle time with C-extension compression cutting execution time up to 37%.
Incremental SAT-PBO ATPG Framework on Berkeley ABC
Apr 2025 β Jun 2025
VLSI Testing
- Developed an incremental SAT+PBO-based ATPG framework in Berkeley ABC, adding custom commands for fault modeling and equivalence fault collapsing to minimize test set size.
- Validated on the c17 ISCAS85 benchmark, achieving fewer test patterns than PODEM with 100% fault coverage via the Kissat SAT solver.
